Year after year, more and more users are transferring more and more data wirelessly. To keep up with this trend and make data transfer faster and more efficient, the fifth generation of mobile communications (5G) is being rolled out, and the industry is already looking to the future. 5G can achieve peak data rates of 10Gbit/s, while 6G is expected to operate at 100Gbit/s from 2030. In addition to dealing with more data and connectivity, researchers are also looking at how next-generation wireless communications can support new use cases such as autonomous driving and holographic presence.
In order to achieve extremely high data rates, the telecommunications industry has been increasing the frequency of wireless signals. While 5G will initially use bands below 6GHz, products targeting 28/39 GHZ have been demonstrated. In addition, due to the FR3 (6-20GHz) band's ability to balance coverage and capacity, there is growing interest in using the FR3 (6-20GHz) band for 5G networks. For 6G, frequencies above 100GHz are being discussed.
Moving to higher frequencies has several advantages: new bands can be used and spectrum scarcity within existing bands can be addressed. Moreover, the higher the operating frequency, the easier it is to obtain a wider bandwidth. In principle, frequencies above 100GHz and bandwidths up to 30GHz allow telecom operators to use low-order modulation schemes in wireless data links, thereby reducing power consumption. Higher frequencies are also associated with smaller wavelengths (λ). As the antenna array size scales with λ 2, the antenna array can be arranged more densely. This contributes to better beamforming, a technique that ensures that most of the transmitted energy reaches the target receiver.
But the higher frequency comes at a cost. Today, CMOS is the technology of choice for building key components of transmitters and receivers. These include a power amplifier within the front module for sending RF signals to or from the antenna. The higher the operating frequency, the more difficult it is for a CMOs-based power amplifier to deliver the required output power with a high enough efficiency.
This is where technologies such as GaN and InP come into play. Due to their excellent material properties, these III/V semiconductors are more likely to deliver the desired output power and efficiency at high operating frequencies. For example, GaN has a high current density, high electron mobility, and a large breakdown voltage. The high power density also enables smaller form factors, thereby reducing the overall system size with the same performance.
GaN and InP are superior to CMOS at higher operating frequencies
In modeling experiments, imec researchers compared the performance of three different power amplifier implementations at 140GHz operating frequencies: an all-CMOS implementation, a CMOS beamformer with a SiGe heterojunction bipolar transistor (HBT), and an InP HBT. InP clearly wins in terms of output power (over 20dBm) and energy efficiency (20 to 30 percent). The modeling results also show that for InP, the sweet spot for energy efficiency is obtained with a relatively small number of antennas. This is especially interesting for use cases with limited footprint, such as user devices, such as mobile devices.
Figure 1 - Compare the power consumption of CMOS, SiGe, and InP devices in transmitter architectures with the number of antennas (as described in IEDM 2022).
However, GaN exhibits excellent performance at lower millimeter-wave frequencies. For 28GHz and 39GHz, high electron mobility transistors (HEMTs) made of gallium nitride (GaN-on-SiC) on silicon carbide outperformed CMOs-based devices and GaAs HEMTs in terms of output power and energy efficiency. Two different use cases are considered, namely fixed wireless access (FWA, with 16 antennas) and user devices (with 4 antennas).
Figure 2 - (left) FWA and (right) Output power at 28 GHZ and 39GHz operating frequencies in user devices: a comparison of the three different technologies (as shown on IEDM 2022).
Opportunities and challenges of upgrading
But if we consider cost and ease of integration, GaN and InP device technologies are not yet fully competitive with CMOs-based technologies. III/V devices are typically manufactured on small and expensive non-silicon substrates, relying on processes that are less suited to high-volume manufacturing. Integrating these devices on 200 or 300mm silicon wafers is an interesting way to achieve overall optimization while maintaining superior RF performance. Silicon substrates are not only cheaper, but CMOS-compatible processes can also enable large-scale manufacturing.
Integrating GaN and InP on Si platforms requires the incorporation of new transistor and circuit design methods, materials, and manufacturing techniques. One of the main challenges is related to large lattice mismatches: 8% InP and 17% GaN. It is well known that this creates many defects in the layer and ultimately degrades device performance.
In addition, we must integrate GaN-on-Si and InP-on-Si based components together with CMOs-based components into a complete system. GaN and InP technologies will initially be used to implement power amplifiers within front end modules. In addition, low-noise amplifiers and switches may benefit from the unique properties of these compound semiconductors. But ultimately, CMOS is still needed for calibration, control, and beamforming.
In its advanced RF program, imec, together with its industry partners, explores various ways to integrate GaN and InP devices on large-size silicon wafers and how to achieve their heterogeneous integration with CMOS components. The pros and cons of different use cases (infrastructure (such as FWA) as well as user devices) are being evaluated.
Improve the RF performance of GaN-on-Si technology
Depending on the starting substrate, there are several types of GaN technologies: GaN bulk substrates, Gan-on-sic, and Gan-on-Si. Today, GaN-on-SiC is widely explored and has been used in infrastructure applications, including 5G base stations. Gan-on-sic is more cost-effective than GaN bulk substrates technology, and silicon carbide is an excellent thermal conductor that helps dissipate heat generated in high-power infrastructure applications. However, the cost and limited substrate size make it less suitable for mass production.
In contrast, GaN-on-Si has the potential to scale up to 200mm or even 300mm wafers. Thanks to many years of innovation in power electronics applications, the integration of GaN on large Si substrates has made great progress. However, the silicon-based gallium nitride technology needs to be further improved to achieve optimal RF performance. The main challenge is to achieve large signal and reliability performance comparable to GaN-on-SiC and to increase the operating frequency. This requires continuous innovation in material stack design and material selection, shortening the gate length of HEMTs, suppressing parasitic effects, and keeping RF dispersion as low as possible.
Imec's RF GaN-on-Si process begins with an epitaxial structure grown (by metal-organic chemical vapor deposition (MOCVD)) on a 200mm Si wafer. The structure consists of a proprietary GaN/AlGaN buffer structure, GaN channel, AlN spacer and AlGaN barrier. GaN HEMT devices with TiN Schott group gates are then integrated with the (low-temperature) 3-stage Cu post-process.
Recently, imec's GaN-on-Si platform achieved competitive results, with output power and power added efficiency (PAE) approaching GaN-on-SiC technology for the first time. PAE is a common metric used to evaluate the efficiency of a power amplifier, which takes into account the effect of the amplifier's gain on its overall efficiency.
Figure 3 - silicon-based gallium nitride benchmark data. The red IMEC data is one of the best reports for GaN-on-Si devices, comparable to GaN-on-SiC substrates (as described at IEDM 2022).
Complementing technology development through modeling activities will ultimately help achieve better performance and reliability. For example, at IEDM 2022, imec introduced a simulation framework to better predict heat transfer in RF devices. In the case study of a silicon-based gallium nitride HEMT, simulations showed that the peak temperature rise was three times higher than previously predicted. Modeling efforts such as these provide further guidance for optimizing RF devices and their layout early in the development phase.
InP-on-Si for 6G Asia-Pacific Hertz frequencies: Three manufacturing methods
As mentioned earlier, the InP HBT offers the best output power/efficiency trade-off at 140GHz operating frequencies achieved by all technologies. The researchers also know how to design the InP HBT for optimal RF performance. But manufacturing usually starts with small (InP) substrate wafers (< 150mm) using laboratory-like processes that are incompatible with CMOS. But what happens to performance when we integrate InP on Si? Deposition of InP on Si is known to introduce a number of defects, mainly threading dislocations and planar defects. These defects can cause leakage currents that can greatly degrade device performance or cause reliability problems.
Three upgrade approaches are being considered. Two of them rely on direct growth of InP on Si, and the other relies on wafer reconfiguration. All three approaches are expected to provide a more cost-effective solution than existing technologies using small InP substrates. But they all have their pros and cons in terms of performance, cost, and potential for heterogeneous integration. Imec takes on the role of assessing the advantages and challenges of various use cases (infrastructure as well as mobile devices).
Figure 4 - Schematic diagram of different InP-on-Si growth methods: (a) nano-ridge engineering; (b) blanket growth with strain relaxed buffers, and (c) wafer reconstruction.
The first method of manufacturing INP-on-Si HBT (Figure 4b) uses a strain-relaxation buffer layer deposited directly on top of Si to compensate for the 8% lattice mismatch between Si and InP. Next, InP grows directly on top of this buffer layer. The ability to use larger wafer sizes, especially where part of the silicon can be reused, provides a significant cost advantage. However, optimizations are needed to further reduce the number of defects.
In contrast to this "blanket" growth method, imec proposes nano-ridge engineering(NRE) as an alternative technology to deal with defects more effectively (Figure 4a). NRE relies on selective growth of Group III/V materials in pre-patterned grooves in Si. These high aspect ratio grooves are very effective for trapping defects in narrow bottoms and allow high-quality, low-defect material to be grown outside the grooves. The overgrown nano-ridge widens it toward the top, forming a solid base for the device stack. The initial insights gained from the GaAs/InGaP case study will guide the optimization of the target InGaAs/InP NRE HBT device.
In addition to growing directly, INPs can also be placed on Si using wafer reconstruction techniques (Figure 4c). In this case, a high-quality InP substrate (with or without an active layer) is cut into slices during wafer construction. These tiles are then attached to silicon wafers using a chip-to-wafer bonding technique. The main challenges lie in the efficient transfer of materials and the removal of InP substrates, for which several technologies are being considered.
Strike heterogeneous integration
Ultimately, the III/V-on-Si power amplifier must be combined with a CMOs-based component responsible for functions such as calibration and control. Imec is investigating various heterogeneous integration options, weighing their advantages and disadvantages in various use cases. Advanced laminated substrate technology is the most common way to integrate different RF components into system-level packages and is being optimized to accommodate higher frequencies.
In addition, imec is exploring more advanced heterogeneous integration options, including 2.5D mediation layers and 3D integration technologies. Especially for frequencies above 100GHz, it is important to note that the antenna module starts to define the area where the transceiver can be used. In fact, when the frequency is higher, the wavelength decreases, and the area of the antenna array shrinks accordingly. Above 100GHz, the antenna size becomes smaller than the front-end module size, which hardly shrinks with increasing frequency. For large antenna array configurations, an interesting option is to move the RF front-end module below the antenna array. This is where 3D integration technologies (die-to-wafer or and wafer-to-wafer) come into play, enabling short and clear connections between the front end module and the antenna module. However, thermal management is still an important issue for 3D integration, and being able to provide an effective heat sink is critical. At imec, we are conducting a comprehensive System Technology Collaborative Optimization (STCO) analysis to evaluate different technologies for 3D integration and guide technology selection from a system-level perspective.
For handheld devices, reducing the number of antennas could loosen restrictions, and 2.5D interposer technology is considered an interesting approach. This heterogeneous integration option uses layer stacks with lithographically defined connections, or even through-silicon holes, to communicate between III/V - and CMOs-based components. In this case, the III/V device is located next to the CMOS chip, allowing for better thermal management as both chips can be in direct contact with the heat sink. However, this architecture allows only one-dimensional beam control. We are currently evaluating hardware implementations of 2.5D intermediate layer technology, investigating the best combination of substrate, dielectric and redistribution layer to minimize losses. For example, we demonstrated the first version of RF custom silicon interlayer technology, which uses a standard silicon substrate, copper semi-addition interconnect.
Figure 5 - Schematic illustration of an RF Si interpolator with integrated InP and CMOS devices and antenna array in the package.
Together, recent upgrades and integration efforts show that silicon-based gallium nitride and silicon-based indium phosphide can be viable technologies for the next generation of high-capacity wireless communications applications.