Nowadays, the research and development of the most advanced large computing power chips is showing a "competition" of building blocks. Whoever's "dismantling" and "piecing together" program is superior, who has a better chance to win a place in the market. With the continuous fermentation of the chiplet concept, chiplet architecture and heterogeneous computing have gradually evolved from the occasional surprise of the head manufacturer to the new normal of high-performance chips.
Interface: Chiplet interconnect key
In high-performance computing and artificial intelligence applications, as the size of SOCs has approached reticle size, designers have been forced to split SOCs into smaller chips and package them together. These decomposed dies require interconnections between dies with ultra-short distances and high data rates. In addition to bandwidth, the connection between die and die must be reliable and have extremely low latency and power efficiency.
Die-to-Die Interface definition
Die-to-die interface is a functional module that provides a data interface between two dies in the same package. It provides a reliable, high-bandwidth inter-chip interconnection method, so that different dielet can connect and work together at the system level. In order to achieve power and high bandwidth, they take advantage of the features of extremely short channels connecting the bare pieces. A Die-to-die interface usually consists of a PHY and a controller module, establishing a reliable data connection between the internal structure of the two Dies. Without a die-to-die interface, communication between Dies becomes very difficult.
Example of a high-performance computing and server SoC requiring die-to-die connectivity （source:eetimes）
The past and present lives of the Chiplet architecture
Die-to-die interface, as an interconnection technology, was born to support the design of chiplet. The chiplet architecture behind it is driven by application requirements and has undergone three iterations of development.
1. Isomorphic splitting: First, it is the iteration of cost. Large SOCs are split into multiple homogeneous Dies of the same design, which flow separately, thereby increasing manufacturing efficiency and reducing costs. Case in point: AMD Zen/Zen+, which achieves a 40% cost reduction with unchanged performance.
2. Isomorphic expansion: Then, performance improvement. By splicing more functional units together, horizontal expansion, to achieve higher computing power and memory capacity; This is very beneficial for AI training tasks dealing with large-scale neural networks and massive amounts of data.
Example of an AI SoC requiring die-to-die connectivity（source:eetimes）
A typical example is Tesla DoJo. In the Dojo chip system, the D1 chip is the basic computing unit (chiplet) of the Dojo system. Each Dojo contains 25 D1 and 40 dedicated IO chips, which are integrated together using TSMC's System-on-wafer technology. Achieve large computing power support.
3. Modular heterogeneous combination: With the development of chiplet to 3D architecture, chiplet gradually evolved modular units and differentiated into functional die and interconnect die unit types. Common functional die such as CPU, GPU, Senser, Wireless, photoelectric and other modules, focusing on different tasks and functions; Interconnected dies usually contain some key hardware components to enable high-speed data transfer and communication between functional dies. By combining chip modules with different functions, it helps the chip to be more flexible and easier to achieve expansion and customization.
High speed interconnect core IO Die
High-speed interconnect core IO Die is a dielet independent of the CPU core chip. The IO Die usually contains various functional modules responsible for interconnection, which are responsible for the interconnection of other functional units. In AMD's Zen 2 architecture, the separate IO Die design was adopted for the first time, which was a major milestone in the Chiplet architecture.
Overall, the IO die design can improve system performance, reliability and scalability, and can reduce manufacturing costs and power consumption. In addition, IO die can choose the most suitable process nodes, do not have to follow the CPU Core to adopt the most advanced process nodes, and can do a large iteration every two or three generations of processor updates.
Industry ecological pattern changes
Since the development of Chiplet ecology, we have seen its development process as a new technology, from internal self-research to open:
1. Internal self-research: In the early development of Chiplet technology, large chip manufacturers such as AMD began to test the water of chiplet, but it is often limited to independent research and development and application within enterprises, and only applied to some high-end products, such as servers and high-performance computing, and there are still technical bottlenecks in assembly and testing.
2. Semi-open period: At present, with the continuous maturity and commercialization of chiplet technology, more and more chip manufacturers, design companies and packaging and testing manufacturers begin to pay attention to and use chiplet technology. Chiplet is used in a growing range of processors, accelerators, chipsets, and memory, from high-performance servers to miniaturized electronics. Assembly and testing technology has also been further improved and perfected; In addition, chiplet technology related products and services continue to emerge in the market, chiplet as a chip technology, its commercial application trend has also promoted the upgrade and development of the entire chip ecosystem.
3. Full openness: With the development of chiplet technology, more and more industrial chain companies will emerge in the future, focusing on all aspects of the chiplet industrial chain, that is, the complete chiplet ecological chain consisting of chiplet system level design, EDA/IP, core (core, non-core, IO Die, Base Die), manufacturing, and encapsulation.
Chiplet, a new industry with high hopes
According to the "2022-2027 Chiplet Industry Venture Capital Situation and Investment and Financing Strategy Guidance Report" released by Xinsi Industry Research Center, at present, Chiplet technology is mainly used in autonomous driving, data centers, consumer electronics, high-performance computing, high-end smart chips and other fields. With the development of downstream industries, Chiplet has a broad market prospect. It is expected that in 2025-2035, the global Chiplet market size will grow from $6.5 billion to $60 billion, and the industry development has entered a stage of rapid growth.
However, Chiplet is still an integrated technology in essence, and there are a series of technical difficulties related to integration such as interconnection and heat dissipation. At the same time, several core technologies involved in Chiplet, such as chip design, EDA/IP, packaging technology, are either missing or in the early stage of technological development, and the domestic ecology has not been established. And this series of work is very challenging. Fortunately, China is also working to build a more comprehensive and open Chiplet ecosystem. In December 2022, at the second China Interconnect Technology and Industry Conference, the first group standard "Small Chip Interface Bus Technical Requirements" jointly developed by relevant enterprises and experts in the field of integrated circuits in China was officially approved and released by the China Electronics Industry Standardization Technology Association of the Ministry of Industry and Information Technology.
This standard describes the Chiplet technical requirements for applications such as cpus, Gpus, artificial intelligence chips, network processors, and network switching chips. On the basis of forming the broad design division around Chiplet design, this standard also facilitates the formation of Chiplet standards.
The development and rise of Chiplet technology is not only the need of technical development, but also the drive of economic law. In short, the chip industry is actively exploring Chiplet technology to balance this rising R&D investment with declining shipments. Looking around at the moment, in the process of developing advanced technologies, we can cheer, we can be excited, but there must be no opportunistic psychology. At present, domestic manufacturers can only be down-to-earth, face the difficulties, and always.