If we had one word to describe our future, it would be "data-centric."
Today, there is an explosion of data at every level in almost every industry. Every second, our digital world generates 4,000 terabytes of data, and that amount is only expected to increase in the future. Data-rich applications such as machine learning and artificial intelligence are key data drivers for a wide range of applications such as data centres, 5G and self-driving cars. To run these applications, a powerful processor is needed, based on Si based integrated circuits (ics).
For decades, IC vendors such as Intel designed chips that integrated everything on the same chip, however, as the industry saw a slowdown in Moore's Law (chip density no longer doubled every two years), microscaling single chips became increasingly difficult and expensive. This pushes IC suppliers towards "advanced semiconductor packaging".
What is advanced semiconductor packaging?
Source: Advanced Semiconductor Packaging 2023-2033
Generally speaking, semiconductor packaging is the last two steps in the fabrication and testing of semiconductor devices. In the case of encapsulated IC, the IC nude is encapsulated in a support housing with electrical contacts. In this way, the housing protects the IC bare chip from physical damage and corrosion and connects the IC to PCB boards and other devices. Semiconductor packaging has been around for decades -- the first mass production of semiconductor packaging was in the early 1970s. So, what's new?
As mentioned earlier, due to the slowing down of Moore's Law and the significant increase in monolithic IC manufacturing costs, IC suppliers need new ways to design processors to achieve high performance while remaining cost effective. A new design called "microchips" is a major trend of the future.
The idea behind chiplets was to "split" a single piece of IC into multiple functional blocks, reassemble the functional blocks into separate chiplets, and then "reassemble" them at the encapsulation level. Ideally, a processor based on a small chip design should have the same or higher performance than a monolithic IC, but with a lower total production cost. Packaging methods, especially those used to connect multiple small chips, play a crucial role in small chip design because they affect the performance of the entire system. These packaging technologies, including 2.5D IC, 3D IC, and high-density fan-out wafer-level packaging, are classified as "advanced semiconductor packaging."
Advanced packaging techniques are essential
Advanced semiconductor packaging technology is critical due to the slowing down of Moore's Law and the rising cost of developing and manufacturing monolithic Si ics. Initially, components were individually packaged and integrated at the PCB board level, but as devices became smaller and required higher processing power, component integration needed to go beyond the board level. Package-level integration is the first advance, followed by wafer level integration, which offers at least tenfold higher connection density, smaller size for size-sensitive applications, and superior performance.
The size of the convex pitch for different packaging technologies offered by different companies.
Wafer level integration includes fan-in, core fan-out, high-density fan-out, 2.5D IC, and 3D IC packaging technologies. However, only those technologies with convex point spacing sizes less than 100 µm are considered "advanced" semiconductor packaging technologies. This includes high-density fan-out, 2.5D IC, and 3D IC packaging technologies. The transition from 2.5D hybrid integration to full 3D vertical integration will be critical for the future of data-centric applications, and we will focus on this transition in this article.
The main challenge in transitioning from 2.5D to 3D was scaling the size of the raised point spacing. In a 2.5D IC package, the size of the bump spacing is between 25 µm and 40 µm, depending on the intermediate layer material. However, for 3D stacked packages, the bump size must be reduced to single-digit µm or even smaller to less than 1 µm. TSMC reports that the stack N7/N6 chips are spaced 9 µm apart, and the stack N5 chips are spaced 6 µm apart. For the N3 chip stack, this is expected to decrease further to 4.5µm and continue to decrease in future generations of ics. Stacking two chips with small bump spacing dimensions is a major challenge because high precision alignment of the bonded dielectric material must be achieved, especially at low temperatures. In addition, the Cu filling material must be properly controlled to prevent spilling during bonding. In addition, for packages with small bump sizes, thermal management becomes a critical issue, which requires consideration of package designs that enable better heat transfer and possibly liquid cooling techniques.
Growth drivers for advanced packaging
IDTechEx identified four main application areas for advanced semiconductor packaging: High performance computing (HPC) applications/data centers, communications networks, autonomous vehicles, and consumer electronics. The growing demand for data processing is a major driver of growth in these applications. However, each application has specific requirements that require different advanced semiconductor packaging technologies.
For HPC applications/data centers, the priority is to provide superior data processing capabilities, which makes 2.5DIC technologies using Si mediation layers or Si Bridges preferred despite their higher cost. In contrast, consumer electronics such as smartphones or smartwatches focus on miniaturization and cost, and organic packaging technology is preferred.
In 5G and beyond, the key challenge is transmission loss. Therefore, advanced packaging technology is used to bring the antenna closer to the RF IC chip, thus minimizing transmission loss. "Packaged antenna (AiP)" is currently the most viable option for 5G millimeter waves, while "Antenna on Chip/Wafer (AoP)" is still under development to reduce costs. For future autonomous vehicles, heterogeneous integration of cpus and other components, such as HBMS and reliable power transmission systems, will create new opportunities for advanced semiconductor packaging and innovation.
The expansion of data processing is the unifying growth factor for all these applications. However, because each application area has different requirements, advanced semiconductor packaging technologies are being used to meet specific requirements.