Ever since IBM and MOTOROLA introduced the first BGA packages in the 1980s, the semiconductor industry has been innovating with new advanced packages. Traditional packaging technologies mainly use lead bonding technology to connect systems, while advanced packaging technologies realize electrical connections by means of Bumping. With the increasing demand for high computing power and integration of downstream applications, advanced packaging technology becomes an important development trend in the future.
Advanced packaging development background
Post-moore's Law is based on Moore's Law, a rule of thumb coined by Gordon Moore, one of Intel's founders, which states that the number of transistors that can fit on an integrated circuit doubles every 18 months or so. In other words, processor performance doubles every two years.
However, as the transistor characteristic size shrinks to less than 10nm, the cost of chip development and manufacturing based on Moore's law will also increase geometrically, and Moore's law will continue to encounter a bottleneck. The industry has proposed More Moore, More than Moore and new devices (Beyond CMOS), where Beyond Moore means not only by further reducing the size of transistors to achieve Moore's law, but through circuit design optimization or advanced packaging process.
Classification of advanced packaging technology
Advanced packaging is the interleaving and aggregation of advanced connection technology, operation unit and packaging idea, which can be divided into three representative advanced packaging technologies, such as Flip-chip, wafer-level Chip size packaging (WLCSP) and system-level packaging (SiP).
1) Flip clip: Different from the traditional lead bonding method, flip process is to deposit directly on the chip I/O pad or deposit convex blocks after wiring, and then turn the chip over for heating, so that the molten solder is combined with the substrate or frame, and the electrical side of the chip is facing down.
It can be further subdivided into flip chip ball raster array package (FCBGA) and Flip chip Size package (FCCSP), among which FCBGA has a high market share and is widely used in notebook computers, high performance computing (HPC) and AI.
2) Wafer level chip size packaging: a new packaging technology that integrates chip size packaging (CSP) and wafer level packaging (WLP). Compared with conventional packaging, wafer level packaging has obvious cost advantages. According to the technology type, wafer-level chip size packaging can be divided into fan-in wafer-level packaging (FIWLP) and fan-out wafer-level packaging (FOWLP).
Due to its smaller package size, fan-in wafer level packages are widely used in power management chips, serial flash memory, RF transceivers, microprocessors, and wireless charging chips.
3) System-level packaging: a variety of chips with different functions are packaged together in parallel or stacking mode. System-level packaging can significantly reduce the package volume, further improve the package density, improve the signal transmission speed and reduce the power consumption, so it is regarded as an important path to achieve beyond Moore's Law.
Because of the advantages of system level packaging in heterogeneous integration, the consumer electronics which emphasizes the combination of portability and functionality is its biggest application field.
Democratizing chip design
Probably the most interesting shift driven by advanced packaging options is the democratization of chip design. PCB design engineers are proficient in layout and packaging of standard components, and upon inspection, it is clear that many of the same skills apply to package design of 2.5D and 3D integrated circuits. The design software used in these applications will still require some productivity gains, but the workflow will still reflect the workflow used in the PCB design.
The basic concept and PCB design is basically the same; The layout engineer constructs the intermediate layer substrate to make the required connections on the embedded component and the attached pipe core. The layout engineer only needs to obtain pin assignments that connect the core to the embedded component. They then use the wiring engine in the CAD tool to make the required connections in the mediation layer and substrate, and finally design the BGA package that will connect to the PCB.
Perhaps it is time for the semiconductor industry to invent a new business model to support this advanced packaging approach. This packaging design approach will be feasible when layout engineers can choose standardized bare pieces for their new components instead of pre-packaged chips located on the PCB. Time will tell if the industry's innovators will step up to build this ecosystem and create the software needed to mass produce these components, but it will expand the role of PCB designers into a new realm, giving them greater control over the devices they produce.